EISA bus
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EISA bus

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This file is intended to provide a basic functional overview of the EISA Bus, so that hobbyists and amateurs can design their own EISA compatible cards.

 198 pin (62+36/62+38) EISA EDGE
198 pin (62+36/62+38) EISA EDGE connector  at the computer (as a sample, wrong numbering)

EISA=Extended Industry Standard Architecture.
The EISA Bus originated in 1988 & 1989. It was developed by the AST, Compaq, Epson, Hewlett-Packard, NEC, Olivetti, Tandy, Wyse and Zenith as an alternative to IBM"s "patented" Micro Channel bus. It received limited use in 386 and 486 based Personal Computers through about 1995 before being obsoleted by the PCI bus as Pentium based systems were introduced.

This file is intended to provide a basic functional overview of the EISA Bus, so that hobbyists and amateurs can design their own EISA compatible cards.

It is not intended to provide complete coverage of the EISA standard.

EISA is an acronym for Extended Industry Standard Architecture. It is an extension of the ISA architecture, which is a standardized version of the bus originally developed by IBM for their PC computers. EISA is upwardly compatible, which means that cards originally designed for the 8 bit IBM bus (often referred to as the XT bus) and cards designed for the 16 bit bus (referred to as the AT bus, and also as the ISA bus), will work in an EISA slot. EISA specific cards will not work in an AT or an XT slot.

The EISA connector uses multiple rows of connectors. The upper row is the same as a regular ISA slot, and the lower row contains the EISA extension. The slot is keyed so that ISA cards cannot be inserted to the point where they connect with the EISA signals.

+---------------------------------------------+
|            (component side)                 |
|                                             |
|___________ ISA-16bit __       ISA-8bit    __|
            |||||||||||  |||||||||||||||||||  A1(front)/B1(back)
             | | | | |    | | | | | | | | |  EISA: E1(front)/F1(back)
                   C1/D1
                  G1/H1
A,C,E,G=Component Side
A,B,F,H=Sold Side
Pin Name Description
E1CMD#Command Phase
E2START#Start Phase
E3EXRDYEISA Ready
E4EX32#EISA Slave Size 32
E5GNDGround
E6KEYAccess Key
E7EX16#EISA Slave Size 16
E8SLBURST#Slave Burst
E9MSBURST#Master Burst
E10W/R#Write/Read
E11GNDGround
E12RESReserved
E13RESReserved
E14RESReserved
E15GNDGround
E16KEYAccess Key
E17BE1#Byte Enable 1
E18LA31#Latchable Addressline 31
E19GNDGround
E20LA30#Latchable Addressline 30
E21LA28#Latchable Addressline 28
E22LA27#Latchable Addressline 27
E23LA25#Latchable Addressline 25
E24GNDGround
E25KEYAccess Key
E26LA15Latchable Addressline 15
E27LA13Latchable Addressline 13
E28LA12Latchable Addressline 12
E29LA11Latchable Addressline 11
E30GNDGround
E31LA9Latchable Addressline 9
F1GNDGround
F2+5V+5 VDC
F3+5V+5 VDC
F4---
F5---
F6KEYAccess Key
F7---
F8---
F9+12V+12 VDC
F10M/IO#Memory/Input-Output
F11LOCK#Lock bus
F12RESReserved
F13GNDGround
F14RESReserved
F15BE3#Byte Enable 3
F16KEYAccess Key
F17BE2#Byte Enable 2
F18BE0#Byte Enable 0
F19GNDGround
F20+5V+5 VDC
F21LA29#Latchable Addressline 29
F22GNDGround
F23LA26#Latchable Addressline 26
F24LA24#Latchable Addressline 24
F25KEYAccess Key
F26LA16Latchable Addressline 16
F27LA14Latchable Addressline 14
F28+5V+5 VDC
F29+5V+5 VDC
F30GNDGround
F31LA10Latchable Addressline 10
G1LA7Latchable Addressline 7
G2GNDGround
G3LA4Latchable Addressline 4
G4LA3Latchable Addressline 3
G5GNDGround
G6KEYAccess Key
G7D17Data 17
G8D19Data 19
G9D20Data 20
G10D22Data 22
G11GNDGround
G12D25Data 25
G13D26Data 26
G14D28Data 28
G15KEYAccess Key
G16GNDGround
G17D30Data 30
G18D31Data 31
G19MREQxMaster Request
H1LA8Latchable Addressline 8
H2LA6Latchable Addressline 6
H3LA5Latchable Addressline 5
H4+5V+5 VDC
H5LA2Latchable Addressline 2
H6KEYAccess Key
H7D16Data 16
H8D18Data 18
H9GNDGround
H10D21Data 21
H11D23Data 23
H12D24Data 24
H13GNDGround
H14D27Data 27
H15KEYAccess Key
H16D29Data 29
H17+5V+5 VDC
H18+5V+5 VDC
H19MAKxMaster Acknowledge

EISA is an acronym for Extended Industry Standard Architecture. It is an extension of the ISA architecture, which is a standardized version of the bus originally developed by IBM for their PC computers. EISA is upwardly compatible, which means that cards originally designed for the 8 bit IBM bus (often referred to as the XT bus) and cards designed for the 16 bit bus (referred to as the AT bus, and also as the ISA bus), will work in an EISA slot. EISA specific cards will not work in an AT or an XT slot.

The EISA connector uses multiple rows of connectors. The upper row is the same as a regular ISA slot, and the lower row contains the EISA extension. The slot is keyed so that ISA cards cannot be inserted to the point where they connect with the EISA signals.

Signal Descriptions

+5, -5, +12, -12

Power supplies. -5 is often not implemented.

AEN

Address Enable. This is asserted when a DMAC has control of the bus. This prevents an I/O device from responding to the I/O command lines during a DMA transfer.

BALE

Bus Address Latch Enable. The address bus is latched on the rising edge of this signal. The address on the SA bus is valid from the falling edge of BALE to the end of the bus cycle. Memory devices should latch the LA bus on the falling edge of BALE.

BCLK

Bus Clock, 33% Duty Cycle. Frequency Varies. 8.33 MHz is specified as the maximum, but many systems allow this clock to be set to 10 MHz and higher.

BE(x)

Byte Enable. Indicates to the slave device which bytes on the data bus contain valid data. A 16 bit transfer would assert BE0 and BE1, for example, but not BE2 or BE3.

CHCHK

Channel Check. A low signal generates an NMI. The NMI signal can be masked on a PC, externally to the processor (of course). Bit 7 of port 70(hex) (enable NMI interrupts) and bit 3 of port 61 (hex) (recognition of channel check) must both be set to zero for an NMI to reach the cpu.

CHRDY

Channel Ready. Setting this low prevents the default ready timer from timing out. The slave device may then set it high again when it is ready to end the bus cycle. Holding this line low for too long can cause problems on some systems. CHRDY and NOWS should not be used simultaneously. This may cause problems with some bus controllers.

CMD

Command Phase. This signal indicates that the current bus cycle is in the command phase. After the start phase (see START), the data is transferred during the CMD phase. CMD remains asserted from the falling edge of START until the end of the bus cycle.

SD0-SD16

System Data lines. They are bidrectional and tri-state.

DAKx

DMA Acknowledge.

DRQx

DMA Request.

EX16

EISA Slave Size 16. This is used by the slave device to inform the bus master that it is capable of 16 bit transfers.

EX32

EISA Slave Size 32. This is used by the slave device to inform the bus master that it is capable of 32 bit transfers.

EXRDY

EISA Ready. If this signal is asserted, the cycle will end on the next rising edge of BCLK. The slave device drives this signal low to insert wait states.

IO16

I/O size 16. Generated by a 16 bit slave when addressed by a bus master.

IORC

I/O Read Command line.

IOWC

I/O Write Command line.

IRQx

Interrupt Request. IRQ2 has the highest priority.

LAxx

Latchable Address lines.

LOCK

Asserting this signal prevents other bus masters from requesting control of the bus.

MAKx

Master Acknowledge for slot x: Indicates that the bus master request (MREQx) has been granted.

MASTER16

16 bit bus master. Generated by the ISA bus master when initiating a bus cycle.

M/IO

Memory/Input-Output. This is used to indicate whether the current bus cycle is a memory or an I/O operation.

M16

Memory Access, 16 bit

MRDC

Memory Read Command line.

MREQx

Master Request for Slot x: This is a slot specific request for the device to become the bus master.

MSBURST

Master Burst. The bus master asserts this signal in response to SLBURST. This tells the slave device that the bus master is also capable of burst cycles.

MWTC

Memory Write Command line.

NOWS

No Wait State. Used to shorten the number of wait states generated by the default ready timer. This causes the bus cycle to end more quickly, since wait states will not be inserted. Most systems will ignore NOWS if CHRDY is active (low). However, this may cause problems with some bus controllers, and both signals should not be active simultaneously.

OSC

Oscillator, 14.318 MHz, 50% Duty Cycle. Frequency varies.

REFRESH

Refresh. Generated when the refresh logic is bus master.

RESDRV

This signal goes low when the machine is powered up. Driving it low will force a system reset.

SA0-SA19

System Address Lines, tri-state.

SBHE

System Bus High Enable, tristate. Indicates a 16 bit data transfer.

SLBURST

Slave Burst. The slave device uses this to indicate that it is capable of burst cycles. The bus master will respond with MSBURST if it is also capable of burst cycles.

SMRDC

Standard Memory Read Command line. Indicates a memory read in the lower 1 MB area.

SMWTC

Standard Memory Write Commmand line. Indicates a memory write in the lower 1 MB area.

START

Start Phase. This signal is low when the current bus cycle is in the start phase. Address and M/IO signals are decoded during this phase. Data is transferred during the command phase (indicated by CMD).

TC

Terminal Count. Notifies the cpu that that the last DMA data transfer operation is complete.

W/R

Write or Read. Used to indicate if the current bus cycle is a read or a write operation.

Source:www.pinouts.ru


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